The present invention relates to electronic circuits, and more particularly, to programmable supply voltage regulators for oscillator circuits.
A phase-locked loop (PLL) is an electronic circuit that generates one or more periodic (clock) output signals. A PLL adjusts the frequency of a feedback signal from the output of an oscillator to match in phase the frequency of an input reference clock signal. Phase-locked loops (PLLs) are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions.